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si864x data sheet low-power quad-channel digital isolators silicon lab's family of ultra-low-power digital isolators are cmos devices offering sub- stantial data rate, propagation delay, power, size, reliability, and external bom advantag- es over legacy isolation technologies. the operating parameters of these products re- main stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. all device versions have schmitt trigger inputs for high noise immunity and only require vdd bypass capacitors. data rates up to 150 mbps are supported, and all devices achieve propagation delays of less than 10 ns. enable inputs provide a single point control for enabling and disabling output drive. ordering options include a choice of isolation ratings (1.0, 2.5, 3.75 and 5 kv) and a selectable fail-safe operating mode to control the default output state during power loss. all products >1 kv are safety certified by ul, csa, vde, and cqc, and products in wide-body packages support reinforced insulation withstanding up to 5 kv rms . applications ? industrial automation systems ? medical electronics ? hybrid electric vehicles ? isolated switch mode supplies ? isolated adc, dac ? motor control ? power inverters ? communications systems safety regulatory approvals ? ul 1577 recognized ? up to 5000 v rms for 1 minute ? csa component notice 5a approval ? iec 60950-1, 61010-1, 60601-1 (reinforced insulation) ? vde certification conformity ? si864xxt options certified to reinforced vde 0884-10 ? all other options certified to iec 60747-5-5 and reinforced 60950-1 ? cqc certification approval ? gb4943.1 key features ? high-speed operation ? dc to 150 mbps ? no start-up initialization required ? wide operating supply voltage ? 2.5C5.5 v ? up to 5000 v rms isolation ? reinforced vde 0884-10, 10 kv surge- capable (si864xxt) ? 60-year life at rated working voltage ? high electromagnetic immunity ? ultra low power (typical) 5 v operation ? 1.6 ma per channel at 1 mbps ? 5.5 ma per channel at 100 mbps 2.5 v operation ? 1.5 ma per channel at 1 mbps ? 3.5 ma per channel at 100 mbps ? tri-state outputs with enable ? schmitt trigger inputs ? selectable fail-safe mode ? default high or low output (ordering option) ? precise timing (typical) ? 10 ns propagation delay ? 1.5 ns pulse width distortion ? 0.5 ns channel-channel skew ? 2 ns propagation delay skew ? 5 ns minimum pulse width ? transient immunity 50 kv/s ? aec-q100 qualification ? wide temperature range ? C40 to 125 c ? rohs-compliant packages ? soic-16 wide body ? soic-16 narrow body ? qsop-16 silabs.com | smart. connected. energy-friendly. rev. 2.0
1. ordering guide table 1.1. ordering guide for valid opns 1, 2 ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side max data rate (mbps) default output state isolation rating (kv) temp (c) package si8640ba-b-iu 4 0 150 low 1.0 C40 to 125 c qsop-16 si8640bb-b-is1 4 0 150 low 2.5 C40 to 125 c nb soic-16 si8640bb-b-is 4 0 150 low 2.5 C40 to 125 c wb soic-16 si8640bc-b-is1 4 0 150 low 3.75 C40 to 125 c nb soic-16 si8640ec-b-is1 4 0 150 high 3.75 C40 to 125 c nb soic-16 si8640bd-b-is 4 0 150 low 5.0 C40 to 125 c wb soic-16 si8640ed-b-is 4 0 150 high 5.0 C40 to 125 c wb soic-16 si8641ba-b-iu 3 1 150 low 1.0 C40 to 125 c qsop-16 si8641ba-c-iu 3 1 150 low 1.0 C40 to 125 c qsop-16 si8641bb-b-iu 3 1 150 low 2.5 C40 to 125 c qsop-16 si8641bb-b-is1 3 1 150 low 2.5 C40 to 125 c nb soic-16 si8641bb-b-is 3 1 150 low 2.5 C40 to 125 c wb soic-16 si8641bc-b-is1 3 1 150 low 3.75 C40 to 125 c nb soic-16 si8641ec-b-is1 3 1 150 high 3.75 C40 to 125 c nb soic-16 si8641bd-b-is 3 1 150 low 5.0 C40 to 125 c wb soic-16 si8641ed-b-is 3 1 150 high 5.0 C40 to 125 c wb soic-16 si8642ba-b-iu 2 2 150 low 1.0 C40 to 125 c qsop-16 si8642ba-c-iu 2 2 150 low 1.0 C40 to 125 c qsop-16 si8642ea-b-iu 2 2 150 high 1.0 C40 to 125 c qsop-16 si8642bb-b-is1 2 2 150 low 2.5 C40 to 125 c nb soic-16 si8642bb-b-is 2 2 150 low 2.5 C40 to 125 c wb soic-16 si8642bc-b-is1 2 2 150 low 3.75 C40 to 125 c nb soic-16 si8642ec-b-is1 2 2 150 high 3.75 C40 to 125 c nb soic-16 si8642bd-b-is 2 2 150 low 5.0 C40 to 125 c wb soic-16 SI8642ED-B-IS 2 2 150 high 5.0 C40 to 125 c wb soic-16 si8645ba-b-iu 4 0 150 low 1.0 C40 to 125 c qsop-16 si8645ba-c-iu 4 0 150 low 1.0 C40 to 125 c qsop-16 si8645bb-b-iu 4 0 150 low 2.5 C40 to 125 c qsop-16 si8645bb-b-is1 4 0 150 low 2.5 C40 to 125 c nb soic-16 si8645bb-b-is 4 0 150 low 2.5 C40 to 125 c wb soic-16 si8645bc-b-is1 4 0 150 low 3.75 C40 to 125 c nb soic-16 si8645bd-b-is 4 0 150 low 5.0 C40 to 125 c wb soic-16 si864x data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 2.0 | 1
ordering part number (opn) number of inputs vdd1 side number of inputs vdd2 side max data rate (mbps) default output state isolation rating (kv) temp (c) package product options with reinforced vde 0884-10 rating with 10 kv surge capability si8640bt-is 4 0 150 low 5.0 C40 to 125 c wb soic-16 si8640et-is 4 0 150 high 5.0 C40 to 125 c wb soic-16 si8641bt-is 3 1 150 low 5.0 C40 to 125 c wb soic-16 si8641et-is 3 1 150 high 5.0 C40 to 125 c wb soic-16 si8642bt-is 2 2 150 low 5.0 C40 to 125 c wb soic-16 si8642et-is 2 2 150 high 5.0 C40 to 125 c wb soic-16 si8645bt-is 4 0 150 low 5.0 C40 to 125 c wb soic-16 si8645et-is 4 0 150 low 5.0 C40 to 125 c wb soic-16 note: 1. all packages are rohs-compliant with peak reflow temperatures of 260 c according to the jedec industry standard classifica- tions and peak solder temperatures. 2. si and si are used interchangeably. 3. an "r" at the end of the part number denotes tape and reel packaging option. si864x data sheet ordering guide silabs.com | smart. connected. energy-friendly. rev. 2.0 | 2
2. system overview 2.1 theory of operation the operation of an si864x channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si864x channel is shown in the figure below. figure 2.1. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the trans- mitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that de- codes the input state according to its rf energy content and applies the result to output b via the output driver. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and improved immunity to magnetic fields. see the following figure for more details. figure 2.2. modulation scheme si864x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 2.0 | 3
2.2 eye diagram the figure below illustrates an eye diagram taken on an si8640. for the data source, the test used an anritsu (mp1763c) pulse pattern generator set to 1000 ns/div. the output of the generator's clock and data from an si8640 were captured on an oscilloscope. the re- sults illustrate that data integrity was maintained even at the high data rate of 150 mbps. the results also show that 2 ns pulse width distortion and 350 ps peak jitter were exhibited. figure 2.3. eye diagram si864x data sheet system overview silabs.com | smart. connected. energy-friendly. rev. 2.0 | 4
3. device operation device behavior during start-up, normal operation, and shutdown is shown in figure 3.1 device behavior during normal operation on page 7 , where uvlo+ and uvloC are the respective positive-going and negative-going thresholds. refer to the following tables to determine outputs when power supply (vdd) is not present and for logic conditions when enable pins are used. table 3.1. si86xx logic operation v i input 1, 2 en input 1, 2, 3, 4 vddi state 1, 5, 6 vddo state 1, 5, 6 v o output 1, 2 comments h h or nc p p h enabled, normal operation. l h or nc p p l x 7 l p p hi-z 8 disabled. x 7 h or nc up p l 9 h 9 upon transition of vddi from unpowered to powered, v o returns to the same state as v i in less than 1 s. x 7 l up p hi-z 8 disabled. x 7 x 7 p up undetermined upon transition of vddo from unpowered to powered, vo returns to the same state as v i within 1 s, if en is in either the h or nc state. upon transition of vddo from unpow- ered to powered, v o returns to hi-z within 1 s if en is l. note: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. en is the enable control input located on the same output side. 2. x = not applicable; h = logic high; l = logic low; hi-z = high impedance. 3. it is recommended that the enable inputs be connected to an external logic high or low level when the si86xx is operating in noisy environments. 4. no connect (nc) replaces en1 on si8640/45. no connect replaces en2 on the si8645. no connects are not internally connec- ted and can be left floating, tied to vdd, or tied to gnd. 5. powered state (p) is defined as 2.5 v < vdd < 5.5 v. 6. unpowered state (up) is defined as vdd = 0 v. 7. note that an i/o can power the die for a given side through an internal diode if its source has adequate current. 8. when using the enable pin (en) function, the output pin state is driven into a high-impedance state when the en pin is disabled (en = 0). 9. see 1. ordering guide for details. this is the selectable fail-safe operating mode (ordering option). some devices have default output state = h, and some have default output state = l, depending on the ordering part number (opn). for default high devi- ces, the data channels have pull-ups on inputs/outputs. for default low devices, the data channels have pull-downs on inputs/ outputs. si864x data sheet device operation silabs.com | smart. connected. energy-friendly. rev. 2.0 | 5
table 3.2. enable input truth part number en1 1 , 2 en2 1, 2 operation si8640 h outputs b1, b2, b3, b4 are enabled and follow the input state. l outputs b1, b2, b3, b4 are disabled and in high impedance state. 3 si8641 h x output a4 enabled and follows the input state. l x output a4 disabled and in high impedance state. 3 x h outputs b1, b2, b3 are enabled and follow the input state. x l outputs b1, b2, b3 are disabled and in high impedance state. 3 si8642 h x outputs a3 and a4 are enabled and follow the input state. l x outputs a3 and a4 are disabled and in high impedance state. 3 x h outputs b1 and b2 are enabled and follow the input state. x l outputs b1 and b2 are disabled and in high impedance state. 3 si8645 outputs b1, b2, b3, b4 are enabled and follow the input state. note: 1. enable inputs en1 and en2 can be used for multiplexing, for clock sync, or other output control. en1, en2 logic operation is summarized for each isolator product in table 2. these inputs are internally pulled-up to local vdd allowing them to be connec- ted to an external logic level (high or low) or left floating. to minimize noise coupling, do not connect circuit traces to en1 or en2 if they are left floating. if en1, en2 are unused, it is recommended they be connected to an external logic level, especially if the si86xx is operating in a noisy environment. 2. x = not applicable; h = logic high; l = logic low. 3. when using the enable pin (en) function, the output pin state is driven into a high-impedance state when the en pin is disabled (en = 0). si864x data sheet device operation silabs.com | smart. connected. energy-friendly. rev. 2.0 | 6
3.1 device startup outputs are held low during powerup until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs. 3.2 undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. both side a and side b each have their own undervoltage lockout monitors. each side can enter or exit uvlo independently. for example, side a unconditionally enters uvlo when v dd1 falls below v dd1(uvloC) and exits uvlo when v dd1 rises above v dd1(uvlo+) . side b operates the same as side a with respect to its v dd2 supply. figure 3.1. device behavior during normal operation 3.3 layout recommendations to ensure safety in the end-user application, high-voltage circuits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low-voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). table 4.6 insulation and safety-related specifications on page 21 and table 4.8 iec 60747-5-5 insulation characteristics for si86xxxx 1 on page 22 detail the working volt- age and creepage/clearance capabilities of the si86xx. these tables also detail the component standards (ul1577, iec60747, csa 5a), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. refer to the end- system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1 supply bypass the si864x family requires a 0.1 f bypass capacitor between v dd1 and gnd1 and v dd2 and gnd2. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, the user may also include resistors (50C300 ) in series with the inputs and outputs if the system is excessively noisy. 3.3.2 output pin termination the nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on- chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance pcb traces. 3.4 fail-safe operating mode si86xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input supply is unpowered) can either be a logic high or logic low when the output supply is powered. see table 3.1 si86xx logic operation on page 5 and 1. ordering guide for more information. si864x data sheet device operation silabs.com | smart. connected. energy-friendly. rev. 2.0 | 7
3.5 typical performance characteristics the typical performance characteristics depicted in the following diagrams are for information purposes only. refer to 4. electrical specifications for actual specification limits. figure 3.2. si8640/45 typical vdd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 3.3. si8640/45 typical vdd2 supply current vs. data rate 5, 3.3, and 2.5 v figure 3.4. si8641 typical vdd1 supply current vs. data rate 5, 3.3, and 2.5 v operation figure 3.5. si8641 typical vdd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 3.6. si8642 typical vdd1 or vdd2 supply current vs. data rate 5, 3.3, and 2.5 v operation (15 pf load) figure 3.7. propagation delay vs. temperature (5.0 v data) si864x data sheet device operation silabs.com | smart. connected. energy-friendly. rev. 2.0 | 8
4. electrical specifications table 4.1. recommended operating conditions parameter symbol min typ max unit ambient operating temperature 1 t a C40 25 125 1 c supply voltage v dd1 2.5 5.5 v v dd2 2.5 5.5 v note: 1. the maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. table 4.2. electrical characteristics 1 parameter symbol test condition min typ max unit vdd undervoltage threshold vdd uv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdd uvC v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd undervoltage hysteresis vdd hys 50 70 95 mv positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold vtC all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level output voltage v oh loh = C4 ma v dd1 , v dd2 C 0.4 4.8 v low level output voltage v ol lol = 4 ma 0.2 0.4 v input leakage current si864xxa/b/c/d si864xxt i l 10 15 a output impedance 2 z o 50 enable input current si864xxa/b/c/d si864xxt i enh , i enl v enx = v ih or v il 2.0 10.0 a dc supply current (all inputs 0 v or at supply) si8640bx, ex, si8645bx v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.0 2.4 6.1 2.5 1.6 3.8 9.2 4.0 ma si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 9
parameter symbol test condition min typ max unit si8641bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.4 2.3 5.2 3.6 2.2 3.7 7.8 5.4 ma si8642bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.8 1.8 4.4 4.4 2.9 2.9 6.6 6.6 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 3.6 2.9 5.0 4.0 ma si8641bx, ex v dd1 v dd2 3.4 3.3 4.8 4.6 ma si8642bx, ex v dd1 v dd2 3.3 3.3 4.6 4.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 3.6 4.0 5.0 5.6 ma si8641bx, ex v dd1 v dd2 3.7 4.1 5.2 5.8 ma si8642bx, ex v dd1 v dd2 3.9 3.9 5.4 5.4 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 3.6 17.5 5.0 22.8 ma si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 10
parameter symbol test condition min typ max unit si8641bx, ex v dd1 v dd2 7.3 14.3 9.8 18.5 ma si8642bx, ex v dd1 v dd2 11 11 14.3 14.3 ma timing characteristics si864xbx, ex maximum data rate 0 150 mbps minimum pulse width 5.0 ns propagation delay t phl , t plh see figure 4.2 propagation delay timing on page 13 5.0 8.0 13 ns pulse width distortion |tplh C tphl| pwd see figure 4.2 propagation delay timing on page 13 0.2 4.5 ns propagation delay skew 3 t psk(p-p) 2.0 4.5 ns channel-channel skew t psk 0.4 2.5 ns all models output rise time t r c l = 15 pf see figure 4.2 propagation delay timing on page 13 2.5 4.0 ns output fall time t f c l = 15 pf see figure 4.2 propagation delay timing on page 13 2.5 4.0 ns peak eye diagram jitter t jit(pk) see figure 2.3 eye diagram on page 4 350 ps common mode transient immunity si86xxxa/b/c/d si86xxxt cmti v i = v dd or 0 v v cm = 1500 v see figure 4.3 common- mode transient immunity test circuit on page 13 35 60 50 100 kv/s enable to data valid t en1 see figure 4.1 enable tim- ing diagram on page 13 6.0 11 ns enable to data tri-state t en2 see figure 4.1 enable tim- ing diagram on page 13 8.0 12 ns input power loss to valid default output t sd see figure 3.1 device behav- ior during normal operation on page 7 8.0 12 ns start-up time 4 t su 15 40 s si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 11
parameter symbol test condition min typ max unit note: 1. v dd1 = 5 v 10%; v dd2 = 5 v 10%, t a = C40 to 125 c 2. the nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled-impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the application of power to the appearance of valid data at the output. si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 12
figure 4.1. enable timing diagram figure 4.2. propagation delay timing figure 4.3. common-mode transient immunity test circuit si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 13
table 4.3. electrical characteristics 1 parameter symbol test condition min typ max unit vdd undervoltage threshold vdd uv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdd uvC v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd undervoltage hysteresis vdd hys 50 70 95 mv positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold vtC all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level output voltage v oh loh = C4 ma v dd1 , v dd2 C 0.4 3.1 v low level output voltage v ol lol = 4 ma 0.2 0.4 v input leakage current si864xxa/b/c/d si864xxt i l 10 15 a output impedance 2 z o 50 enable input current si864xxa/b/c/d si864xxt i enh , i enl v enx = v ih or v il 2.0 10.0 a dc supply current (all inputs 0 v or at supply) si8640bx, ex, si8645bx v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.0 2.4 6.1 2.5 1.6 3.8 9.2 4.0 ma si8641bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.4 2.3 5.2 3.6 2.2 3.7 7.8 5.4 ma si8642bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.8 1.8 4.4 4.4 2.9 2.9 6.6 6.6 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 14
parameter symbol test condition min typ max unit si8640bx, ex, si8645bx v dd1 v dd2 3.6 2.9 5.0 4.0 ma si8641bx, ex v dd1 v dd2 3.4 3.3 4.8 4.6 ma si8642bx, ex v dd1 v dd2 3.3 3.3 4.6 4.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 3.6 3.4 5.0 4.7 ma si8641bx, ex v dd1 v dd2 3.5 3.6 4.9 5.1 ma si8642bx, ex v dd1 v dd2 3.6 3.6 5.0 5.0 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 3.6 12.3 5.0 15.9 ma si8641bx, ex v dd1 v dd2 5.9 10.3 7.9 13.4 ma si8642bx, ex v dd1 v dd2 8.2 8.2 10.7 10.7 ma timing characteristics si864xbx, ex maximum data rate 0 150 mbps minimum pulse width 5.0 ns propagation delay t phl , t plh see figure 4.2 propagation delay timing on page 13 5.0 8.0 13 ns si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 15
parameter symbol test condition min typ max unit pulse width distortion |tplh C tphl| pwd see figure 4.2 propagation delay timing on page 13 0.2 4.5 ns propagation delay skew 3 t psk(p-p) 2.0 4.5 ns channel-channel skew t psk 0.4 2.5 ns all models output rise time t r c l = 15 pf see figure 4.2 propagation delay timing on page 13 2.5 4.0 ns output fall time t f c l = 15 pf see figure 4.2 propagation delay timing on page 13 2.5 4.0 ns peak eye diagram jitter t jit(pk) see figure 2.3 eye diagram on page 4 350 ps common mode transient immunity si86xxxa/b/c/d si86xxxt cmti v i = v dd or 0 v v cm = 1500 v see figure 4.3 common- mode transient immunity test circuit on page 13 35 60 50 100 kv/s enable to data valid t en1 see figure 4.1 enable timing diagram on page 13 6.0 11 ns enable to data tri-state t en2 see figure 4.1 enable timing diagram on page 13 8.0 12 ns input power loss to valid default output t sd see figure 3.1 device be- havior during normal opera- tion on page 7 8.0 12 ns start-up time 4 t su 15 40 s note: 1. v dd1 = 3.3 v 10%; v dd2 = 3.3 v 10%, t a = C40 to 125 c 2. the nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled-impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the application of power to the appearance of valid data at the output. si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 16
table 4.4. electrical characteristics 1 parameter symbol test condition min typ max unit vdd undervoltage threshold vdd uv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdd uvC v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd undervoltage hysteresis vdd hys 50 70 95 mv positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold vtC all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 v low level input voltage v il 0.8 v high level output voltage v oh loh = C4 ma v dd1 , v dd2 C 0.4 2.3 v low level output voltage v ol lol = 4 ma 0.2 0.4 v input leakage current si864xxa/b/c/d si864xxt i l 10 15 a output impedance 2 z o 50 enable input current si864xxa/b/c/d si864xxt i enh , i enl v enx = v ih or v il 2.0 10.0 a dc supply current (all inputs 0 v or at supply) si8640bx, ex, si8645bx v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.0 2.4 6.1 2.5 1.6 3.8 9.2 4.0 ma si8641bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.4 2.3 5.2 3.6 2.2 3.7 7.8 5.4 ma si8642bx, ex v dd1 v dd2 v dd1 v dd2 v i = 0(bx), 1(ex) v i = 0(bx), 1(ex) v i = 1(bx), 0(ex) v i = 1(bx), 0(ex) 1.8 1.8 4.4 4.4 2.9 2.9 6.6 6.6 ma 1 mbps supply current (all inputs = 500 khz square wave, ci = 15 pf on all outputs) si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 17
parameter symbol test condition min typ max unit si8640bx, ex, si8645bx v dd1 v dd2 3.6 2.9 5.0 4.0 ma si8641bx, ex v dd1 v dd2 3.4 3.3 4.8 4.6 ma si8642bx, ex v dd1 v dd2 3.3 3.3 4.6 4.6 ma 10 mbps supply current (all inputs = 5 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 3.6 3.1 5.0 4.3 ma si8641bx, ex v dd1 v dd2 3.5 3.4 4.8 4.8 ma si8642bx, ex v dd1 v dd2 3.4 3.4 4.8 4.8 ma 100 mbps supply current (all inputs = 50 mhz square wave, ci = 15 pf on all outputs) si8640bx, ex, si8645bx v dd1 v dd2 3.6 9.9 5.0 12.8 ma si8641bx, ex v dd1 v dd2 5.2 8.5 7.0 11.1 ma si8642bx, ex v dd1 v dd2 6.9 6.9 9.0 9.0 ma timing characteristics si864xbx, ex maximum data rate 0 150 mbps minimum pulse width 5.0 ns propagation delay t phl , t plh see figure 4.2 propagation delay timing on page 13 5.0 8.0 14 ns si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 18
parameter symbol test condition min typ max unit pulse width distortion |tplh -tphl| pwd see figure 4.2 propagation delay timing on page 13 0.2 5.0 ns propagation delay skew 3 t psk(p-p) 2.0 5.0 ns channel-channel skew t psk 0.4 2.5 ns all models output rise time t r c l = 15 pf see figure 4.2 propagation delay timing on page 13 2.5 4.0 ns output fall time t f c l = 15 pf see figure 4.2 propagation delay timing on page 13 2.5 4.0 ns peak eye diagram jitter t jit(pk) see figure 2.3 eye diagram on page 4 350 ps common mode transient immunity si86xxxa/b/c/d si86xxxt cmti v i = v dd or 0 v v cm = 1500 v see figure 4.3 common- mode transient immunity test circuit on page 13 35 60 50 100 kv/s enable to data valid t en1 see figure 4.1 enable timing diagram on page 13 6.0 11 ns enable to data tri-state t en2 see figure 4.1 enable timing diagram on page 13 8.0 12 ns input power loss to valid default output t sd see figure 3.1 device be- havior during normal opera- tion on page 7 8.0 12 ns start-up time 4 t su 15 40 s note: 1. v dd1 = 2.5 v 5%; v dd2 = 2.5 v 5%, t a = C40 to 125 c 2. the nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled-impedance pcb traces. 3. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 4. start-up time is the time period from the application of power to the appearance of valid data at the output. si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 19
table 4.5. regulatory information 1, 2, 3, 4 for all product options except si864xxt csa the si864x is certified under csa component acceptance notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. 60601-1: up to 125 v rms reinforced insulation working voltage; up to 380 v rms basic insulation working voltage. vde the si864x is certified according to iec 60747-5-5. for more details, see file 5006301-4880-0001. 60747-5-5: up to 1200 vpeak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. ul the si864x is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si864x is certified under gb4943.1-2011. for more details, see certificates cqc13001096110 and cqc13001096239. rated up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. for all si864xxt product options csa certified under csa component acceptance notice 5a. for more details, see file 232873. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. vde certified according to vde 0884-10. ul certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc certified under gb4943.1-2011 rated up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. note: 1. regulatory certifications apply to 2.5 kv rms rated devices, which are production tested to 3.0 kv rms for 1 s. 2. regulatory certifications apply to 3.75 kv rms rated devices, which are production tested to 4.5 kv rms for 1 s. 3. regulatory certifications apply to 5.0 kv rms rated devices, which are production tested to 6.0 kv rms for 1 s. 4. for more information, see the ordering guide. si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 20
table 4.6. insulation and safety-related specifications parameter symbol test condition value unit wb soic-16 nb soic-16 qsop-16 nominal air gap (clearance) 1 l(io1) 8.0 4.9 3.6 mm nominal external tracking (creepage) 1 l(io2) 8.0 4.01 3.6 mm minimum internal gap (internal clearance) 0.014 0.014 0.014 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 v rms erosion depth ed 0.019 0.019 0.031 mm resistance (input-output) 2 r io 10 12 10 12 10 12 capacitance (input-output) 2 c io f = 1 mhz 2.0 2.0 2.0 pf input capacitance 3 c i 4.0 4.0 4.0 pf note: 1. the values in this table correspond to the nominal creepage and clearance values. vde certifies the clearance and creepage limits as 4.7 mm minimum for the nb soic-16 package and qsop-16 packages and 8.5 mm minimum for the wb soic-16 package. ul does not impose a clearance and creepage minimum for component-level certifications. csa certifies the clearance and creepage limits as 3.9 mm minimum for the nb soic-16, 3.6 mm for qsop-16 packages, and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si86xx is converted into a 2-terminal device. pins 1C8 are shorted together to form the first termina and pins 9C16 are shorted together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 4.7. iec 60664-1 ratings parameter test conditions specification wb soic-16 nb soic-16 qsop-16 basic isolation group material group i i i installation classification rated mains voltages < 150 v rms i-iv i-iv i-iv rated mains voltages < 300 v rms i-iv i-iii i-iii rated mains voltages < 400 v rms i-iii i-ii i-ii rated mains voltages < 600 v rms i-iii i-ii i-ii si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 21
table 4.8. iec 60747-5-5 insulation characteristics for si86xxxx 1 parameter symbol test condition characteristic unit wb soic-16 nb soic-16 qsop-16 maximum working insulation voltage v iorm 1200 630 630 vpeak input to output test voltage v pr method b1 (v iorm x 1.875 = vpr, 100% production test, t m = 1 sec, partial discharge < 5 pc) 2250 1182 1182 vpeak transient overvoltage v iotm t = 60 sec 6000 6000 6000 vpeak surge voltage v iosm tested per iec 60065 with surge voltage of 1.2 s/50 s si864xxt tested with magnitude 6250 v x 1.6 = 10 kv si864xxb/c/d tested with 4000 v 6250 4000 4000 4000 vpeak pollution degree (din vde 0110, table 1) 2 2 2 insulation resistance at t s , v io = 500 v r s >10 9 >10 9 >10 9 note: 1. maintenance of the safety data is ensured by protective circuits. the si86xxxx provides a climate classification of 40/125/21. table 4.9. iec safety limiting values 1 parameter symbol test condition max unit wb soic-16 nb soic-16 qsop-16 case temperature t s 150 150 150 c safety input, output, or supply current i s ja = 100 c/w (wb soic-16) 105 c/w (nb soic-16, qsop-16) v i = 5.5 v, t j = 150 c, t a = 25 c 220 210 210 ma device power dissipation 2 p d 275 275 275 mw note: 1. maximum value allowed in the event of a failure; also see the thermal derating curve in figure 4.4 (wb soic-16) thermal derat- ing curve, dependence of safety limiting values with case temperature per din en 60747-5-5/vde 0884-10, as applies on page 23 and figure 4.5 (nb soic-16, qsop-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-5/vde 0884-10, as applies on page 23 . 2. the si86xx is tested with vdd1 = vdd2 = 5.5 v; t j = 150 oc; c l = 15 pf, input a 150 mbps 50% duty cycle square wave. si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 22
table 4.10. thermal characteristics parameter symbol wb soic-16 nb soic-16/qsop-16 unit ic junction-to-air thermal resistance ja 100 105 c/w figure 4.4. (wb soic-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-5/vde 0884-10, as applies figure 4.5. (nb soic-16, qsop-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-5/vde 0884-10, as applies si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 23
table 4.11. absolute maximum ratings 1 parameter symbol min max unit storage temperature 2 t stg C65 150 c operating temperature t a C40 125 c junction temperature t j 150 c supply voltage v dd1 , v dd2 C0.5 7.0 v input voltage v i C0.5 v dd + 0.5 v output voltage v o C0.5 v dd + 0.5 v output current drive channel i o 10 ma lead solder temperature (10 s) 260 c maximum isolation (input to output) (1 sec) nb soic-16 4500 v rms maximum isolation (input to output) (1 sec) wb soic-16 6500 v rms note: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. exposure to absolute maximum ratings for exteneded peri- ods may degrade performance. 2. vde certifies storage temperature from C40 to 150 c. si864x data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 2.0 | 24
5. pin descriptions vdd1 gnd1 a1 a3 a4 nc gnd1 a2 vdd 2 gnd2 b2 b1 b4 b3 gnd2 en2/nc i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8640/45 v dd1 gnd1 a1 a3 a4 en1 gnd1 a2 vdd 2 gnd2 b2 b1 b4 b3 gnd2 en2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8641 vdd1 gnd1 a1 a3 a4 en1 gnd1 a2 vdd 2 gnd2 b2 b1 b4 b3 gnd2 en2 i s o l a t i o n rf xmitr rf rcvr rf xmitr rf rcvr rf rcvr rf xmitr rf rcvr rf xmitr rf rcvr si8642 name soic-16 pin# type description v dd1 1 supply side 1 power supply. gnd1 2 1 ground side 1 ground. a1 3 digital input side 1 digital input. a2 4 digital input side 1 digital input. a3 5 digital i/o side 1 digital input or output. a4 6 digital i/o side 1 digital input or output. en1/nc 2 7 digital input side 1 active high enable. nc on si8640/45. gnd1 8 1 ground side 1 ground. gnd2 9 1 ground side 2 ground. en2/nc 2 10 digital input side 2 active high enable. nc on si8645. b4 11 digital i/o side 2 digital input or output. b3 12 digital i/o side 2 digital input or output. b2 13 digital output side 2 digital output. b1 14 digital output side 2 digital output. gnd2 15 1 ground side 2 ground. v dd2 16 supply side 2 power supply. note: 1. for narrow-body devices, pin 2 and pin 8 gnd must be externally connected to respective ground. pin 9 and pin 15 must also be connected to external ground. 2. no connect. these pins are not internally connected. they can be left floating, tied to vdd or tied to gnd. si864x data sheet pin descriptions silabs.com | smart. connected. energy-friendly. rev. 2.0 | 25
6. package outline: 16-pin wide body soic the figure below illustrates the package details for the the si864x digital isolator. the table lists the values for the dimensions shown in the illustration. figure 6.1. 16-pin wide body soic si864x data sheet package outline: 16-pin wide body soic silabs.com | smart. connected. energy-friendly. rev. 2.0 | 26
table 6.1. 16-pin wide body soic package diagram dimensions 1 , 2, 3, 4 dimension min max a 2.65 a1 0.10 0.30 a2 2.05 b 0.31 0.51 c 0.20 0.33 d 10.30 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 0 8 aaa 0.10 bbb 0.33 ccc 0.10 ddd 0.25 eee 0.10 fff 0.20 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation aa. 4. recommended reflow profile per jedec j-std-020c specification for small body, lead-free components. si864x data sheet package outline: 16-pin wide body soic silabs.com | smart. connected. energy-friendly. rev. 2.0 | 27
7. land pattern: 16-pin wide body soic the figure below illustrates the recommended land pattern details for the si864x in a 16-pin wide-body soic package. the table lists the values for the dimensions shown in the illustration. figure 7.1. pcb land pattern: 16-pin wide body soic table 7.1. 16-pin wide body soic land pattern dimensions 1, 2 dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 note: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protru- sion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si864x data sheet land pattern: 16-pin wide body soic silabs.com | smart. connected. energy-friendly. rev. 2.0 | 28
8. package outline: 16-pin narrow body soic the figure below illustrates the package details for the si864x in a 16-pin narrow-body soic (so-16). the table lists the values for the dimensions shown in the illustration. figure 8.1. 16-pin narrow body soic si864x data sheet package outline: 16-pin narrow body soic silabs.com | smart. connected. energy-friendly. rev. 2.0 | 29
table 8.1. 16-pin narrow body soic package diagram dimensions 1, 2, 3, 4 dimension min max a 1.75 a1 0.10 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 9.90 bsc e 6.00 bsc e1 3.90 bsc e 1.27 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. si864x data sheet package outline: 16-pin narrow body soic silabs.com | smart. connected. energy-friendly. rev. 2.0 | 30
9. land pattern: 16-pin narrow body soic the figure below illustrates the recommended land pattern details for the si864x in a 16-pin narrow-body soic. the table lists the val- ues for the dimensions shown in the illustration. figure 9.1. pcb land pattern: 16-pin narrow body soic table 9.1. 16-pin narrow body soic land pattern dimensions 1, 2 dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 note: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si864x data sheet land pattern: 16-pin narrow body soic silabs.com | smart. connected. energy-friendly. rev. 2.0 | 31
10. package outline: 16-pin qsop the figure below illustrates the package details for the si864x in a 16-pin qsop package. the table lists the values for the dimensions shown in the illustration. figure 10.1. 16-pin qsop si864x data sheet package outline: 16-pin qsop silabs.com | smart. connected. energy-friendly. rev. 2.0 | 32
table 10.1. 16-pin qsop package diagram dimensions 1, 2, 3, 4 dimension min max a 1.75 a1 0.10 0.25 a2 1.25 b 0.20 0.30 c 0.17 0.25 d 4.89 bsc e 6.00 bsc e1 3.90 bsc e 0.635 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline mo-137, variation ab. 4. recommended card reflow profile is per the jedec/ipc j-std-020d specification for small body components. si864x data sheet package outline: 16-pin qsop silabs.com | smart. connected. energy-friendly. rev. 2.0 | 33
11. land pattern: 16-pin qsop the figure below illustrates the recommended land pattern details for the si864x in a 16-pin qsop package. the table lists the values for the dimensions shown in the illustration. figure 11.1. pcb land pattern: 16-pin qsop table 11.1. 16-pin wide body soic land pattern dimensions 1, 2 dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 0.635 x1 pad width 0.40 y1 pad length 1.55 note: 1. this land pattern design is based on ipc-7351 pattern sop63p602x173-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed. si864x data sheet land pattern: 16-pin qsop silabs.com | smart. connected. energy-friendly. rev. 2.0 | 34
12. top marking: 16-pin wide body soic si86xysv yywwrttttt tw e4 figure 12.1. 16-pin wide body soic top marking table 12.1. 16-pin wide body soic top marking explanation line 1 marking: base part number ordering options (see 1. ordering guide for more information.) si86 = isolator product series x = # of data channels (4) y = # of reverse channels (5, 2, 1, 0) 1 s = speed grade (max data rate) and operating mode: b = 150 mbps (default output = low) e = 150 mbps (default output = high) v = insulation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv; d = 5.0 kv; t = 5.0 kv with 10 kv surge capability. line 2 marking: yy = year ww = workweek assigned by assembly subcontractor. corresponds to the year and workweek of the mold date. rttttt = mfg code manufacturing code from assembly house r indicates revision line 3 marking: circle = 1.7 mm diameter (center-justified) e4 pb-free symbol country of origin iso code ab- breviation tw = taiwan note: 1. si8645 has 0 reverse channels. si864x data sheet top marking: 16-pin wide body soic silabs.com | smart. connected. energy-friendly. rev. 2.0 | 35
13. top marking: 16-pin narrow body soic si86xysv yywwrttttt e3 figure 13.1. 16-pin narrow body soic top marking table 13.1. 16-pin narrow body soic top marking explanation line 1 marking: base part number ordering options (see 1. ordering guide for more information.) si86 = isolator product series x = # of data channels (4) y = # of reverse channels (5, 2, 1, 0) 1 s = speed grade (max data rate) and operating mode: b = 150 mbps (default output = low) e = 150 mbps (default output = high) v = insulation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv line 2 marking: circle = 1.2 mm diameter e3 pb-free symbol yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from assembly house r indicates revision note: 1. si8645 has 0 reverse channels. si864x data sheet top marking: 16-pin narrow body soic silabs.com | smart. connected. energy-friendly. rev. 2.0 | 36
14. top marking: qsop figure 14.1. qsop top marking table 14.1. qsop top marking explanation line 1 marking: base part number ordering options (see 1. ordering guide for more information.) 86 = isolator product series x = # of data channels (4) y = # of reverse channels (5, 2, 1, 0) 1 s = speed grade (max data rate) and operating mode: b = 150 mbps (default output = low) e = 150 mbps (default output = high) v = insulation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv line 2 marking: rttttt = mfg code manufacturing code from assembly house r indicates revision line 3 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. note: 1. si8645 has 0 reverse channels. si864x data sheet top marking: qsop silabs.com | smart. connected. energy-friendly. rev. 2.0 | 37
15. document change list revision 0.1 to revision 0.2 ? added chip graphics on page 1. ? moved tables 1 and 11 to page 18. ? updated table 6, insulation and safety-related specifications, on page 15. ? updated table 8, iec 60747-5-5 insulation characteristics for si86xxxx*, on page 16. ? moved table 1 to page 4. ? moved table 2 to page 5. ? moved typical performance characteristics to page 8. ? updated "3. pin descriptions" on page 9. ? updated "4. ordering guide" on page 10. revision 0.2 to revision 1.0 ? reordered spec tables to conform to new convention. ? removed pending throughout document. revision 1.0 to revision 1.1 ? updated high level output voltage voh to 3.1 v in table 3, electrical characteristics, on page 8. ? updated high level output voltage voh to 2.3 v in table 4, electrical characteristics, on page 11. revision 1.1 to revision 1.2 ? updated table 3, ordering guide for valid opns on page 10. ? updated note 1 with msl2a. ? updated current revision devices. revision 1.2 to revision 1.3 ? updated "4. ordering guide" on page 10 to include msl2a. revision 1.3 to revision 1.4 ? updated table 11 on page 18. ? added junction temperature spec. ? updated "2.3.1. supply bypass" on page 7. ? removed 3.3.2 pin connections on page 23. ? updated "3. pin descriptions" on page 9. ? updated table notes. ? updated "4. ordering guide" on page 10. ? removed rev a devices. ? updated "5. package outline: 16-pin wide body soic" on page 12. ? updated top marks. ? added revision description. revision 1.4 to revision 1.5 ? updated "4. ordering guide" on page 10. ? updated "11.5. top marking (16-pin qsop)" on page 22. revision 1.5 to revision 1.6 ? added figure 3, common mode transient immunity test circuit, on page 7. ? added references to cqc throughout. ? added references to 2.5 kvrms devices throughout. ? updated "4. ordering guide" on page 10. ? updated "11.1. top marking (16-pin wide body soic)" on page 20. si864x data sheet document change list silabs.com | smart. connected. energy-friendly. rev. 2.0 | 38
revision 1.6 to revision 1.7 ? updated table 5 on page 14. ? added cqc certificate numbers. ? updated "4. ordering guide" on page 10. ? added si8640ba opn. ? removed references to moisture sensitivity levels. ? removed note 2. revision 1.7 to revision 1.8 ? added product options si8641bb-b-iu, si8645bb-b-iu and si864xxt in 1. ordering guide . ? added spec line items for input and enable leakage currents pertaining to si864xxt in electrical specifications. ? added new spec for t sd in 4. electrical specifications . ? updated iec 60747-5-2 to iec 60747-5-5 throughout document. revision 1.8 to revision 1.9 november 18, 2015 ? deleted duplicate si8641bb-b-iu opn listing and corrected si8645bb-b-iu listing in 1. ordering guide . ? added qsop-16 information to table 4.7 iec 60664-1 ratings on page 21 . ? added qsop-16 information to table 4.8 iec 60747-5-5 insulation characteristics for si86xxxx 1 on page 22 . ? added qsop-16 information to table 4.9 iec safety limiting values 1 on page 22 . ? added qsop-16 reference to figure 4.5 (nb soic-16, qsop-16) thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-5/vde 0884-10, as applies on page 23 . si864x data sheet document change list silabs.com | smart. connected. energy-friendly. rev. 2.0 | 39
table of contents 1. ordering guide ..............................1 2. system overview ..............................3 2.1 theory of operation ............................3 2.2 eye diagram ..............................4 3. device operation ..............................5 3.1 device startup .............................7 3.2 undervoltage lockout ...........................7 3.3 layout recommendations ..........................7 3.3.1 supply bypass .............................7 3.3.2 output pin termination ..........................7 3.4 fail-safe operating mode ..........................7 3.5 typical performance characteristics ......................8 4. electrical specifications ...........................9 5. pin descriptions ............................. 25 6. package outline: 16-pin wide body soic .................... 26 7. land pattern: 16-pin wide body soic ..................... 28 8. package outline: 16-pin narrow body soic ................... 29 9. land pattern: 16-pin narrow body soic .................... 31 10. package outline: 16-pin qsop ....................... 32 11. land pattern: 16-pin qsop ........................ 34 12. top marking: 16-pin wide body soic ..................... 35 13. top marking: 16-pin narrow body soic .................... 36 14. top marking: qsop ........................... 37 15. document change list .......................... 38 table of contents 40
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